1. Field of the Invention
The present invention is directed to a method of manufacturing a semiconductor device, and more particularly to a novel method of forming minute and fine patterns by a novel sequence of etchings while avoiding the problems encountered in conventional etchings.
2. Description of the Prior Art
Methods for the manufacture of semiconductor devices are being continuously developed, and improved photolithograhic processes for patterning the substrate surface are fundamentally important. As is generally understood, conventional wet etching techniques using chemicals appear to have reached a limit for precision, and extremely minute patterns are now formed by means of dry etching instead. However, very sharp edges and steps are produced by the dry etching which is now practiced.
Technology for the manufacture of integrated circuits is reviewed these days for the purpose of increasing integration density, so that characteristics such as faster speed of operation, lower dissipation of power and so forth may be improved. While patterns formed on the substrate surface tend to become finely miniaturized, there is a new trend to fabricate integrated circuits in multi-layer structures. As the number of layers increase, from three to four, for example, the steps and differences in height between the levels of adjacent layers increase, resulting in differences in the thickness of layers grown on top of these others, such as in the wiring layers and insulation layers. If the wiring layer becomes very thin at a step, breaking of the wiring layer is likely to happen, and if the insulation layer becomes very thin at a step, wiring layers may easily be short-circuited.
Conventional wet etching which cannot produce fine patterns, has proved to be advantageous compared to dry etching when problems resulting from formation of sharp steps are taken into consideration.
In order to produce fine patterns in a wiring layer for example, a dry etching as is practiced recently becomes necessary. For avoiding steps or edges with sharp corners where the wiring or insulation layer is etched or cut through, a conventional wet etching has been found to be advantageous. But, to obtain a tapered or inclined side of the wiring or insulation layer contradicts the purpose of forming fine patterns. Yet, in the fabrication of densely packed integrated circuits, these two must be attained simultaneously.
The object of forming fine patterns has been partially accomplished by miniaturization of windows for electrodes and via holes formed in an insulation film on a semiconductor substrate. FIG. 1 schematically illustrates in cross-section a via hole formed by an isotropic etching in a conventional wet etching device or a barrel type dry etching device. A via hole is formed through an insulation layer 4, of phosphosilicate-glass (PSG) for example, reaching to a wiring layer 3, of say aluminum or polycrystalline silicon, formed on an insulation film 2 grown on a semiconductor substrate 1 such as of silicon. The via hole has an opening which is larger than the window in a photoresist film 5 used as a mask. This indicates that an accurate and fine via hole cannot be formed by the known isotropic etching technique.
A similar problem is also experienced in forming wiring patterns by a conventional isotropic etching. FIG. 2 shows schematically in cross-section wiring patterns 3 formed on an insulating film 2 grown on a semiconductor substrate 1 of say silicon by an isotropic etching according to known art using a photoresist film 5 as a mask. The width of the upper surface of the wiring layer 3 is smaller than the width of the photoresist film 5 used as a mask.
In order to overcome these problems, a planar type plasma etching device was selected to avoid the side etchings inevitable in isotropic etching. If a via hole is etched into the structure of FIG. 1 using a planar type plasma etching device, the insulation layer 4 of PSG is etched in a direction vertical to the surface of the substrate 1 as shown in FIG. 3. The opening of the via hole thus formed is substantially equal to the opening of the photoresist film 5 used as a mask.
However, when the photoresist film 5 is removed and a wiring layer 6 of aluminum for example is patterned on the insulation layer 4, the wiring layer 6 covering the insulation layer 4 has thin portions 7 at the step, as shown in FIG. 4, because the edges of the via hole are sharp.
FIG. 5 illustrates schematically in cross-section two wiring layers fabricated in accordance with conventional techniques. The wiring layer 3 on the insulation film 2 was formed by a planar type plasma etching device and the wiring layer 6 was patterned on the insulation layer 4. It is seen that the wiring layer 6 may be broken at steps 7. This is due to the sharp or sudden steps formed by anisotropic dry etching carried out when the wiring layers 3 were patterned.